User guide

16-16
SWIFT VMC Models and SmartModels
Compiling and Simulating a Model
If your design instantiates a SmartModel or a VMC model, you
compile your design with the -lmc-swift compile-time option. Be
sure to also include the Verilog template file on the vcs command
line. For example:
vcs -lmc-swift xc4062xl_432.swift.v test.v design.v
This command line results in an executable file named simv. Enter
this executable file on a command line to simulate the design that
instantiates the model:
simv
Changing the Timing of a Model
You can enter the +override_model_delays runtime option in
combination with either the +mindelays, +typdelays, or
+maxdelays option to override the DelayRange parameter in the
template file that specifies the timing used by the model.
If you use this method, all the SmartModel models in your design will
use either the minimum, typical, or maximum delays specified by the
+mindelays, +typdelays, or +maxdelays option.
If you want to use different timing options in different models in your
design you must edit the template files for each model to change the
DelayRange parameter definition to either "MIN", "TYP", or
"MAX".