User guide

16-14
SWIFT VMC Models and SmartModels
The following is an example of an initial block that passes commands
through the command channel:
initial
begin
#1 circuit.model.cmd$str = "show doc";
circuit.model.do$model$cmd=1 ; // 1
#1 circuit.model.do$model$cmd=0 ;
#1 circuit.model.cmd$str = "show timing unit";
circuit.model.do$model$cmd = 1;
#1 circuit.model.do$model$cmd=0 ;
#1 circuit.model.cmd$str = "show version";
circuit.model.do$model$cmd = 1;
#1;
end
The Verilog template files for SmartModel memory models also
contain the following reg declarations that allow you to write or dump
the contents of a memory to a file:
For example, if you had a memory model with the hierarchical name
top.asic.mem1 and you wanted to dump its contents to file
mem1.1k.dump at time 1000, and mem1.2k.dump at time 2000, you
could use the following initial block in your test fixture module:
initial
begin
#1000 top.asic.mem1.mem$dump$file = "mem1.1k.dump";
top.asic.mem1.do$mem$dump = 1;
#1000 top.asic.mem1.mem$dump$file = "mem1.2k.dump";
top.asic.mem1.do$mem$dump = 1;
end
mem$dump$file
The reg to which you assign the name of the file into which
the memory model writes its contents. The model writes
to this file when do$mem$dump has a value of 1.
do$mem$dump
Enables writing the memory models contents to the file.