User guide

16-9

SWIFT VMC Models and SmartModels

The following are examples of these regs in the Verilog template file:

//Generating SmartModel Windows data

reg [1:0] GEN_CCLK_SPEED;

reg [4:0] LENGTH_CNT_WIDTH;

reg [10:0] FRAME_SIZE;

reg [12:0] DEVICE_FRAMES;

reg [3:0] CRC_ERROR_CHK;

reg SYNC_TO_DONE;

reg [3:0] DONE_ACTIVE;

reg [3:0] IO_ACTIVE;

reg [3:0] DEVICE_STATE;

reg CONFIGURATIONMODE;

You enable and disable the monitoring of these window regs with the

special $swift_window_monitor_on and

$swift_window_monitor_off system tasks. The syntax for

these system tasks are as follows:

$swift_window_monitor_on("instance_name"[,"window_reg",

"window_reg",...]);

$swift_window_monitor_off("instance_name"[,"window_reg",

"window_reg",...]);

Here:

The following are examples of using these system tasks:

Example 1

$swift_window_monitor_on("test.design.xc4062xl_432_1");

instance_name

Specifies the hierarchical name of the instance of the module

definition in the Verilog template file.

window_reg

The identifier of the window reg in the Verilog template file.

If you do not specify a window reg in these system tasks, you

enable or disable the monitoring of all the window regs in the

instance.