User guide

16-8
SWIFT VMC Models and SmartModels
For more information on SmartModel attributes that are parameters
in the Verilog template file, see the SmartModel Library Simulator
Interface Manual.
Monitoring Signals in the Model Window
SWIFT VMC models and SmartModels can have a window that
enables you to see the values of certain signals inside the model. For
some models you can also deposit values on these signals. The
model-specific data sheet lists which signals that you can monitor in
the window and whether you can also deposit values to these signals.
When you generate the Verilog template file for a model, VCS
declares window regs in the template file that correspond to these
signals inside the model window. By monitoring the window regs, you
monitor the corresponding signals in the model. Assigning values to
these window regs deposits values to the corresponding signals in
the model.
To enable VCS to declare these regs for SmartCircuit models, do the
following:
1. Create the file listing the SmartCircuit windows. Refer to the
SmartModel Library Users Manual for a description of how to do
this.
2. Create a soft link or copy the Model Control File (MCF) to a file
named scf in the current directory. VCS uses this file to load the
netlist for the SmartCircuit model that contains the signals in the
window.