User guide

16-7
SWIFT VMC Models and SmartModels
Redefining Parameters
The Verilog template file contains a number of parameters that are
used for specifying model attributes. In some cases you can modify
the parameter definition. For example, the template file contains the
following parameter definition:
parameter DelayRange = "MAX";
This parameter specifies using the maximum delays of min:typ:max
delay triplets in the model. You can change the definition to "TYP"
or "MIN". There is an alternative to editing the DelayRange
parameter definition; see "Changing the Timing of a Model" on page
16-16.
For another example, the template file for a memory model might
contain the following parameter definition:
parameter MemoryFile = "memory";
If you know that all instances of this model will need to load memory
file mem.dat, you can change this to:
parameter MemoryFile = "mem.dat";
You can also use defparam statements to change these parameter
definitions. For example, if an instance of a memory model has an
instance name of test.design.mem1 and this model must load
memory file mem1.dat, you can enter the following in the test fixture
module:
defparam design.mem1.MemoryFile = "mem1.dat";