User guide

16-6
SWIFT VMC Models and SmartModels
The modifications you can make are as follows:
Reordering ports in the module header
If, for example, the module header is as follows:
module xyz (IO0, IO1, IO2, IO3, IO4);
You can reorder the ports:
module xyz (IO4, IO3, IO2, IO1, IO0);
Concatenating ports in the module header
You can concatenate ports in the module header, for example:
module xyz ({IO4, IO3, IO2, IO1}, IO0);
Doing so enables you to connect vector signals to the model as
follows:
wire [3:0] bus4;
...
xyz xyz1( bus4, ...
Naming concatenation expressions in the module header
In Verilog you can name concatenation expressions in the port
connection list in a module header. For example:
module xyz (.IO({IO4, IO3, IO2, IO1}), IO0);
This allows you to use name based connections in the module
instantiation statement, as follows:
wire [3:0] bus4;
..
xyz xyz1( sig1, .IO(bus4), ...