User guide

16-5
SWIFT VMC Models and SmartModels
This command generates a Verilog template file named
modelname.swift.v. For example, if you enter the following vcs
command:
vcs -lmc-swift-template xc4062xl_432
VCS writes the xc4062xl_432.swift.v file in the current directory.
The Verilog template file contains a Verilog module definition that
contains:
• The special $vcs_swift user-defined system task for the
SWIFT interface that enables you to use the command channel
to the SWIFT interface to pass commands to the model and see
messages from the model.
• Declarations for window regs that enable you to see the value of
and, in some cases, deposit values to signals in the model. See
"Monitoring Signals in the Model Window" on page 16-8.
• Declarations for regs that you use to pass commands to the
model.
• Port and reg declarations and assignment statements that are
part of a Verilog shell for the model.
When you instantiate the module definition in this Verilog template
file, you instantiate the model.
Modifying the Verilog Template File
You can make certain modifications to the contents of the Verilog
template file.