User guide

16-2
SWIFT VMC Models and SmartModels
5. Compile the design with compile-time options for the SWIFT
interface and then simulate your design.
This chapter describes these steps in the following topics:
• SWIFT Environment Variables
• Generating Verilog Templates
• Monitoring Signals in the Model Window
• Using LMTV SmartModel Window Commands
• Entering Commands Using the SWIFT Command Channel
• Loading Memories at the Start of Runtime
• Compiling and Simulating a Model
Note:
The information in this chapter is provided as a convenience to
the Synopsys model user. It includes basic information about
simulating Synopsys models. This chapter is not, however, the
authoritative source on this subject. More complete and
sometimes more up-to-date information can be found in the
Simulator Configuration Guide for Synopsys Models. This guide
is available on-line in PDF format at http://www.synopsys.com/
products/lm/doc/smartmodel/manuals/simcfg.pdf or http://
www.synopsys.com/products/lm/doc/hardwaremodel/manuals/
simcfg.pdf
SWIFT Environment Variables
You set some SWIFT environment variables on all platforms. Others
you set only on certain platforms.