User guide

16-1

SWIFT VMC Models and SmartModels

SWIFT VMC Models and SmartModels 1

VMC models are secure, protected, and portable models of Verilog

designs. They contain no Verilog code. SmartModels are models from

Synopsys that model devices from various vendors. SWIFT is the

interface for both of these kinds of models. VCS enables you to

instantiate both these kinds of models in your design and simulate

them as part of your design. The steps you take are as follows:

1. Set the SWIFT environment variables.

2. Generate a Verilog template file for the model. You use this

template file to instantiate the model.

3. Enable the monitoring of signals inside the model through the

model window.

4. Enter commands for the model in your source code using the

LMTV window commands or the SWIFT command channel.