User guide

15-6
SAIF Support
To generate an SDPD backward SAIF file using a forward SAIF file,
do the following:
initial begin
$read_lib_saif(<inputFile>);
$set_toggle_region(<Scope>);
// initialization of Verilog signals, and then:
$toggle_start;
// testbench
$toggle_stop;
$toggle_report(<outputFile>, timeUnit, <Scope>);
end
To generate a non-SDPD backward SAIF file without using SAIF files,
do the following:
initial begin
$set_gate_level_monitoring("on");
$set_toggle_region(<Scope>);
// initialization of Verilog signals, and then:
$toggle_start;
// testbench
$toggle_stop;
$toggle_report(<outputFile>, timeUnit, <Scope>);
end
Criteria for Choosing Signals for SAIF Dumping
VCS supports only scalar wire and reg, as well as vector wire and
reg, for monitoring. It does not consider wire/reg declared within
functions, tasks and named blocks for dumping. Also, it does not
support bit selects and part selects as arguments to
$set_toggle_region or $toggle_report. In addition, it
monitors cell hiconns based on the policy.