User guide

14-26
Negative Timing Checks
The $setuphold timing checks now specify:
• A violation window for a falling edge on signal d between 40 and
30 time units before a rising edge on signal cp
• A violation window for a rising edge on signal d between 20 and
10 time units before a rising edge on signal cp
The testbench module top applies stimulus so that the following
transitions occur:
1. A rising edge on signal d at time 45
2. A rising edge on signal cp at time 50
The rising edge on signal d a t ti me 4 5 i s n o t i ns i de the violation window
for a rising edge on signal d. If you include the +overlap
compile-time option you will not see a timing violation. This behavior
is what you want because there is no transition in the violation
windows so VCS should not display a timing violation.
The +overlap option tells VCS not to change the violation windows,
just like it would if the windows overlapped.
If you omit the +overlap option VCS does what Verilog simulators
traditionally do, which is both pessimistic and inaccurate:
1. During compilation VCS replaces the -30 and -10 negative delay
values in the $setuphold timing checks with 0 values. It displays
the following warning:
Warning: Negative Timing Check delays did not converge,
Setting minimum constraint to zero and using approximation
solution (
"sourcefile",line_number_of__second_timing_check)