User guide

14-24
Negative Timing Checks
#45 in1=1;
end
initial
begin
clk=0;
#50 clk = 1;
#50 clk = 0;
end
endmodule
module FD1 (d, cp, q);
input d, cp;
output q;
wire q;
reg notifier;
reg q_reg;
always @(posedge cp)
q_reg = d;
assign q = q_reg;
specify
$setuphold( posedge cp, negedge d, 40, 30, notifier);
$setuphold( posedge cp, posedge d, 20, 10, notifier);
endspecify
endmodule
The SDF file contains the following to backannotate negative delay
values:
(CELL
(CELLTYPE "FD1")
(INSTANCE top.fd1_1)
(TIMINGCHECK
(SETUPHOLD (negedge d) (posedge cp) (40) (-30))
(SETUPHOLD (posedge d) (posedge cp) (20) (-10))
)
)