User guide

14-23
Negative Timing Checks
In unusual and rare circumstances multiple $setuphold and
$recrem timing checks, including those that have no negative limits,
can make the delays on the delayed versions of these signals
mutually exclusive. When this happens VCS repeats the following
procedure until the signals are no longer mutually exclusive:
1. Sets one negative limit to 0.
2. Recalculates the delays of the delayed signals.
Using Multiple Non-Overlapping Violation Windows
The +overlap compile-time option enables accurate simulation of
multiple violation windows for the same two signals when the following
conditions occur:
• The violation windows are specified with negative delay values
that are backannotated from an SDF file.
• The violation windows do not converge or overlap.
The default behavior of VCS when these conditions are met is to
replace the negative delay values with zeros so that the violation
windows overlap. Consider the following code example:
‘timescale 1ns/1ns
module top;
reg in1, clk;
wire out1;
FD1 fd1_1 ( .d(in1), .cp(clk), .q(out1) );
initial
begin
$sdf_annotate("overlap1.sdf");
in1 = 0;