User guide

14-9
Negative Timing Checks
delayed_data_signal
The name of the delayed version of the data signal.
The following example demonstrates how to use the extended syntax:
$setuphold(ref, data, -4, 10, notifr1, stampreg===1, , d_ref,
d_data);
In this example, the timestamp_cond argument specifies that reg
stampreg must equal 1 for VCS to “stamp” or record the times of
data events in the setup phase or “stamp” the times of reference
events in the hold phase. If this condition is not met, and stamping
does not occur, VCS will not find timing violations no matter what the
time of these events is. Also in the example, the delayed versions of
the reference and data signals are named d_ref and d_data.
You can use these delayed signal versions of the signals to drive
sequential devices in your cell model. For example:
module DFF(D,RST,CLK,Q);
input D,RST,CLK;
output Q;
reg notifier;
DFF_UDP d2(Q,dCLK,dD,dRST,notifier);
specify
(D => Q) = 20;
(CLK => Q) = 20;
$setuphold(posedge CLK,D,-5,10,notifier,,,dCLK,dD);
$setuphold(posedge CLK,RST,-8,12,notifier,,,dCLK,
dRST);
endspecify
endmodule
primitive DFF_UDP(q,clk,data,rst,notifier);
output q; reg q;
input data,clk,rst,notifier;
table
// clock data rst notifier state q
// ------------------------------
r 0 0 ? : ? : 0 ;