User guide

14-4

Negative Timing Checks

When this happens, use the $setuphold timing check in the

top-level module of the cell to look for timing violations when signal

values propagate to that sequential device. In this case, you need to

use negative setup or hold limits in the $setuphold timing check.

Figure 14-2 ASIC Cell with Long Propagation Delays on Reference Events

When this happens the violation window shifts at the cell boundary

so that it no longer straddles the reference event. It shifts to the right

when there are longer propagation delays on the reference event.

This right shift requires a negative setup limit:

$setuphold (posedge clock, data, -10, 31, notifyreg);

Figure 14-3 illustrates this scenario.

causes

long

delay

causes short delay

clock

data

clk