User guide

14-3

Negative Timing Checks

Figure 14-1 Positive Setup and Hold Limits

Here both the setup and hold limits have positive values. When this

happens the violation window straddles the reference event.

There are cases where the violation window cannot straddle the

reference event at the inputs of an ASIC cell. Such a case occurs

when:

• The data event takes longer than the reference event to propagate

to a sequential device in the cell

• Timing must be accurate at the sequential device

• You need to check for timing violations at the cell boundary

It also occurs when the opposite is true, that is when the reference

event takes longer than the data event to propagate to the sequential

device.

setup

limit

hold

limit

violation window

reference

event

data

event

data

event

clock

data