User guide

13-44
SDF Backannotation
1. Remove the clock signal entries from the timopt.cfg file
2. Recompile the design with the same +timopt+clock_period
compile-time option.
Timopt will write new clock signal entries in the timopt.cfg file.
Editing Clock Signal Entries
The following is an example of the clock signal entries:
clock {
// test.badClock , // 1
test.goodClock // 2000
} {100ns};
These clock signals have a period of 100 ns or longer. This time value
comes from the +clock_period argument that you added to the
+timopt compile-time option when you first compiled the design.
The entry for the signal test.badClock is commented out because it
connects to a small percentage of the sequential devices in the
design, in this case only 1 of the 2001 sequential devices that it
identified in the design. The entry for the signal test.goodClock is not
commented out because it connects to a large percentage of the
sequential devices, in this case 2000 of the 2001 sequential devices
in the design.
If a commented out clock signal is a clock signal that you want
timopt to use when it optimizes the design in a subsequent
compilation, then remove the comment characters from in front of the
signal’s hierarchical name.