User guide

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TetraMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59
Make Accessing an Undeclared Bit an Error Condition . . B-59
Treat Output Ports As Inout Ports . . . . . . . . . . . . . . . . . . B-59
Allow Inout Port Connection Width Mismatches. . . . . . . . B-59
Specifying a VCD File. . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59
Memories and Multi-Dimensional Arrays (MDAs) . . . . . . B-60
Specifying a Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
Hardware Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-61
Changing Source File Identifiers to Upper Case . . . . . . . B-61
Defining a Text Macro. . . . . . . . . . . . . . . . . . . . . . . . . . . . B-61
Specifying the Name of the Executable File. . . . . . . . . . . B-62
Returning The Platform Directory Name . . . . . . . . . . . . . B-62
Specifying Native Code Generation . . . . . . . . . . . . . . . . . B-62
For Long Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-62
Appendix C. Simulation Options
Options for Simulating OpenVera Testbenches . . . . . . . . . . . C-2
Options for Simulating OpenVera Assertions. . . . . . . . . . . . . C-4
Options for SystemVerilog Assertions . . . . . . . . . . . . . . . . . . C-6
Options for a CLI Command File . . . . . . . . . . . . . . . . . . . . . . C-9
Options for Specifying VERA Object Files . . . . . . . . . . . . . . . C-10
Options for Coverage Metrics . . . . . . . . . . . . . . . . . . . . . . . . C-10
Options for Enabling and Disabling Specify Blocks . . . . . . . . C-12
Options for Specifying When Simulation Stops . . . . . . . . . . . C-13
Options for Recording Output . . . . . . . . . . . . . . . . . . . . . . . . C-13
Options for Controlling Messages . . . . . . . . . . . . . . . . . . . . . C-14
Options for Discovery Visual Environment and UCLI . . . . . . C-15
Options for VPD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15