User guide

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Timopt will make the additional optimizations that it did not make
because it was unsure of the signals and sequential devices in
the timopt.cfg file that it wrote during the first compilation.
4. Look at the timopt.cfg file again:
- If timopt wrote no new entries for potential clock signals or
sequential devices, go to step 5.
- If timopt wrote new entries but you make no changes to the
new entries, go to step 5.
- If you make modifications to the new entries, return to step 3.
5. Timopt does not need to look for any more clock signals and it
can assume that the timopt.cfg file correctly specifies clock signal
and sequential devices. Now it just needs to apply the latest
optimizations. Compile your design one more time including the
+timopt compile-time option but without its +clock_period
argument.
6. You now simulate your design using timopt optimizations.
Timopt monitors the simulation. Timopt makes its optimizations
based on its analysis of the design and information in the
timopt.cfg file. If during simulation it finds that its assumptions are
incorrect, for example the clock period for a clock signal is
incorrect, or there is a port for asynchronous control on a module
for a sequential device, timopt displays a warning message like
the following:
+ Timopt Warning: for clock testbench.clockgen..clk:
TimePeriod 50ns Expected 100ns