User guide

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SDF Backannotation
Include the +mindelays compile-time option to specify using the
minimum delay of the min:typ:max delay value triplet either in delay
specification or in the delay value in entries in an SDF file.
Include the +maxdelays compile-time option to specify using the
maximum delay.
By default VCS uses the typical delays. You can specify using the
typical delays with the +typdelays compile-time option.
In the case of SDF files, the mtm_spec argument to the
$sdf_annotate system task overrides the +mindelays,
+typdelays, or +maxdelays options.
Specifying Min:Typ:Max Delays at Runtime
If you have either of the following:
• An SDF file that backannotates delays to your design when
simulation starts and which contains delay values that are
min:typ:max delay value triplets
• Module path delays or timing check delays in your Verilog source
code are min:typ:max delay value triplets
There is a method that enables you to specify using minimum, typical,
or maximum delays at runtime instead of at compile-time.
This method is to use the +allmtm compile-time option and use the
+mindelays, +typdelays, and +maxdelays options at runtime
instead of at compile-time.