User guide

13-25
SDF Backannotation
identifier: verilog_id | identifier_head verilog_id
identifier_head : verilog_id '.' | identifier_head verilog_id '.'
number : "Any sized or unsized literal decimal, octal, binary, hex, or real number"
verilog_id : "Any legal escaped or non-escaped Verilog identifier (excluding
range selection portion in square brackets)."
Example:
MODULE sub {
// scale_commads
SCALE_TYPE=FROM_MTM;
SCALE_FACTORS=1:2:3;
// mtm_commads
MTM=MINIMUM;
// map_inner_commands
MAP_INNER = X;
(i1 *> o1) = IGNORE;
(i *> o1) = ADD { (ib *> oa); }
(i1 *> o1) = ADD { (ia *> oa); }
(i1 *> o1) = ADD { (ia *> oa); }
(i1 *> o1) = ADD { (ib *> ob); }
if (i2==1) (i2 *> o2) = ADD { (ib *> ob); }
}
SDF Example with Configuration File
The following example uses the VCS SDF configuration file sdf.cfg:
// test.v - test sdf annotation
`timescale 1ns/1ps
module test;
initial begin
$sdf_annotate("./test.sdf",test, "./sdf.cfg",,,,);
end
wire out1,out2;
wire w1,w2;
reg in;
reg ctrl,ctrlw;