User guide

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Preventing Mangling of Top-Level Modules. . . . . . . . . . . . . . 25-24
Appendix A. VCS Environment Variables
Simulation Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . A-2
Optional Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . A-3
Appendix B. Compile-Time Options
Options for Accessing Verilog Libraries . . . . . . . . . . . . . . . . . B-4
Options for Incremental Compilation . . . . . . . . . . . . . . . . . . . B-6
Options for Help and Documentation. . . . . . . . . . . . . . . . . . . B-9
Options for SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
Options for OpenVera Native Testbench . . . . . . . . . . . . . . . . B-11
Options for Different Versions of Verilog . . . . . . . . . . . . . . . . B-15
Options for Initializing Memories and Regs . . . . . . . . . . . . . . B-16
Options for Using Radiant Technology. . . . . . . . . . . . . . . . . . B-16
Options for 64-bit Compilation . . . . . . . . . . . . . . . . . . . . . . . . B-16
Options for Debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17
Options for Finding Race Conditions . . . . . . . . . . . . . . . . . . B-20
Options for Starting Simulation Right After Compilation . . . . B-21
Options for Compiling OpenVera Assertions (OVA). . . . . . . . B-22
Options for Compiling For Simulation With Vera . . . . . . . . . . B-23
Options for Compiling For Coverage Metrics. . . . . . . . . . . . . B-23
Options for Discovery Visual Environment and UCLI . . . . . . B-30
Options for Converting VCD and VPD Files . . . . . . . . . . . . . B-31
Options for Specifying Delays . . . . . . . . . . . . . . . . . . . . . . . . B-32
Options for Compiling an SDF File . . . . . . . . . . . . . . . . . . . . B-35