User guide

13-23
SDF Backannotation
| path_declaration = IGNORE ;
The SDF annotator uses hierarchical_path as the Verilog hierarchical
path name of a submodule within module_type. The paths specified
in the SDF file are mapped to module_type. This path applies to all
path delays and timing checks specified for this module in the SDF
file including those mapped with ADD and OVERRIDE.
ADD
Adds to the mapping specifications of the SDF file. The original_
timing specification is mapped to new_timing, the Verilog HDL
syntax of a path delay or timing check.
OVERRIDE
Replaces the mapping specifications of the SDF file. The
original_timing specification is mapped to new_timing, the Verilog
HDL syntax of a path delay or timing check.
IGNORE
Ignores the mapping specifications in the SDF file. In all cases,
the hierarchical_path name is applied to any new_timing
specification before they are annotated to VCS.
list_of_systchk : systchk ';' | list_of_systchk systchk ';'
systchk: '$setup' '(' systchk_arg ',' systchk_arg ',' expression opt_notifier ')'
|'$hold' '(' systchk_arg ',' systchk_arg ',' expression
opt_notifier ')'
|'$setuphold' '(' systchk_arg ',' systchk_arg ',' expression ','
expression opt_notifier ')'
|'$recovery' '(' systchk_arg ',' systchk_arg ',' expression
opt_notifier ')'
|'$period' '(' systchk_arg ',' expression opt_notifier ')'
|'$width' '(' systchk_arg ',' expression ',' expression
opt_notifier ')'
|'$skew' '(' systchk_arg ',' systchk_arg ',' expression
opt_notifier ')'
|'$nochange' '(' systchk_arg ',' systchk_arg ',' expression ','
expression opt_notifier ')'
opt_notifier: ',' expression | ',' | ;
systchk_arg: expression
| expression '&&&' timing_check_condition
| timing_check_event_control specify_terminal_descriptor
| timing_check_event_control specify_terminal_descriptor
'&&&' timing_check_condition