User guide

13-15
SDF Backannotation
VCS does not however backannotate the module path delay values
as specified. Instead VCS backannotates the shorter of the
corresponding delays in the two IOPATH entries. Therefore the
following behavior occurs during simulation when a value propagates
from inport to outport:
• When the value propagation results in a rising edge on outport,
the module path delay from inport to outport is three, no matter
whether the value propagation began with a rising or falling edge
on inport, because three is shorter than five.
• When the value propagation results in a falling edge on outport,
the module path delay from inport to outport is four, no matter
whether the value propagation began with a rising or falling edge
on inport, because four is shorter than six.
In this example there are two delay values in the two IOPATH entries
for the same pair of ports, for a rising and falling edge on the output
or inout port, but VCS would also backannotate the shorter of the
corresponding delay values if the IOPATH entries each had only one
delay value or each had three or six delay values (delay value lists
with 12 values are not implemented).
VCS does this, backannotates the shorter of the corresponding delay
values, to be compatible with the earlier generation of Verilog
simulators, Cadence’s Verilog-XL.
Disabling CELLTYPE Checking in SDF Files
Sometimes when you merge smaller designs into a larger design you
discover that you have more than one module in the larger design
with the same identifier or name. When this happens you must resolve
the conflict by editing your Verilog source code to rename one of the
modules that shares the same identifier.