User guide

13-13
SDF Backannotation
0 0 x
5 0 0
$finish at simulation time 100
V C S S i m u l a t i o n R e p o r t
Time: 100 ns
CPU Time: 0.100 seconds; Data structure size: 0.0Mb
Performance Considerations
Because the compiler must make large quantities of information
about the structure of the design available at run time in order to allow
annotation, you must consider simulation efficiency when using SDF
annotation. Keep in mind the following:
• For annotation capabilities gate, mp, and tchk, there is overhead
only if the modules actually contain the related constructs.
• For module input port delays, significant compile and runtime
overhead can be incurred if annotation is enabled on ports that
will not be annotated.
• Enabling port bit annotation increases the overhead.
Use the %CELL wildcard scope as shown in the previous section (or
%CELL+ if all the annotated cells are below the $sdf_annotate call)
to annotate only those modules that require SDF annotation ACC
capabilities.
Replacing Negative Module Path Delays in SDF Files
VCS does not backannotate negative module path delays from
IOPATH entries in SDF files. By default VCS substitutes a 0 delay for
these negative delays.You can tell VCS to instead use the module
path delay specified in a module’s specify block by including the
+old_iopath compile-time option.