User guide

13-12
SDF Backannotation
end
endmodule
module leaf(in,out);
input in;
output out;
buf(out,in);
specify
specparam mpath_d=1.0;
(in => out) = (mpath_d);
endspecify
endmodule
The following is the SDF file, ex2.sdf, for the Verilog model:
(DELAYFILE
(TIMESCALE 1 ns)
(CELL
(CELLTYPE “leaf”)
(INSTANCE leaf1)
(DELAY
(ABSOLUTE
(IOPATH in out (5))))))
In this file the SDF construct IOPATH corresponds to a Verilog module
path delay. The delay value specified is 5. The time unit, specified by
the TIMESCALE construct, makes the annotated delay value to the
module path delay 5 ns.
The PLI table file, ex2.tab contains the following:
$sdf_annotate call=sdf_annotate_call acc=mp:top+
We specify the PLI table file on the vcs command line:
vcs -P ex2.tab ex2.v
We see the successful backannotation of the delay value when we
execute the simv executable and see transition times and values from
the $monitor system task: