User guide

13-6
SDF Backannotation
input CK, D;
specify
(D *> out) = (1,2);
(CK *> out) = (3);
endspecify
endmodule
module leafB(out,D,CK);
output out;
input D;
input CK;
buf(out,D);
endmodule
The following is the SDF file, ex.sdf, for the Verilog model.
(DELAYFILE
(DESIGN "test")
(VENDOR "")
(DIVIDER .)
(VOLTAGE :1:)
(PROCESS "typical")
(TEMPERATURE:1:)
(TIMESCALE1ns)
(CELL
(CELLTYPE "leafB")
(INSTANCE leaf2)
(DELAY
(ABSOLUTE
(PORT D (1:2:3)))
)
)
(CELL
(CELLTYPE "leafA")
(INSTANCE leaf1)
(DELAY
(ABSOLUTE
(IOPATH D out (7)))