User guide

13-3
SDF Backannotation
Compiling the SDF file, when you compile your Verilog source files,
creates binary data files that VCS reads when it executes a
$sdf_annotate system task at runtime. VCS reads binary data files
much faster than ASCII SDF files. The additional compile time will
always be less than the time saved at run time. There are, however,
limitations on your design when you compile an SDF file. If you cannot
circumvent these limitations you can use the method of telling VCS
to read the ASCII SDF file when it executes a $sdf_annotate system
task.
When you use an SDF file to backannotate delay values you can also
use an SDF configuration file. In this file you can specify, among other
things, the selection of minimal, typical, or maximal delay values in
min:typ:max delay value triplets, and the scaling of these delay
values. You can then specify these delay value operations for your
entire design and on a module by module basis.
Compiling the ASCII SDF File at Compile-Time
At compile time, VCS automatically compiles the SDF file you specify
as the first argument to the $sdf_annotate system task in your
design.
This method saves you simulation time. However, in some cases you
may need to disable the automatic compilation of SDF files with the
+oldsdf compile-time option.
The $sdf_annotate System Task
You use the $sdf_annotate system task to tell VCS to backannotate
delay values from an SDF file to your Verilog design.