User guide

12-21
Delays and Timing
Example 12-11 Conflicting Delay Modes
‘timescale 1 ns / 1 ns
module design (out,in);
output out;
input in;
wire int1,int2;
assign #4 out=int2;
buf #3 buf2 (int2,int1),
buf1 (int1,in);
specify
(in => out) = 7;
endspecify
endmodule
In Example 12-11, the module path delay is seven time units but the
delay specifications distributed along that path add up to ten time
units.
If you include the +delay_mode_path compile-time option, VCS
ignores the delay specifications in the primitive instantiation and
continuous assignment statements and uses only the module path
delay. In Example 12-11, it would use the seven time unit delay for
propagating signal values through the module.
If you include the +delay_mode_distributed compile-time
option, VCS ignores the module path delays and uses the delay in
the delay specifications in the primitive instantiation and continuous
assignment statements. In Example 12-11, it uses the ten time unit
delay for propagating signal values through the module.