User guide

12-4
Delays and Timing
Different Inertial Delay Implementations
For compatibility with the earlier generation of Verilog simulators,
inertial delays have two different implementations, one for primitives
(gates, switches and UDPs), continuous assignments, and MIPDs
(Module Input Port Delays) and the other for module path delays and
INTERCONNECT delays backannotated from an SDF file to a net.
For more details on SDF backannotation, see Chapter 15. There is
also a third implementation that is for module path and
INTERCONNECT delays and pulse control, see "Pulse Control" on
page 12-7.
Inertial Delays for Primitives, Continuous Assignments, and
MIPDs
Both implementations were devised to filter out narrow pulses but the
one for primitives, continuous assignments, and MIPDs can produce
unexpected results. For example, Figure 12-3 shows the waveforms
for nets connected to the input and output terminals of a buf gate
with a delay of five time units.
In this implementation there can never be more than one scheduled
event on an output terminal. To filter out narrow pulses, the trailing
edge of a pulse can alter the value change but not the transition time
of the event scheduled by the leading edge of the pulse if the event
has not yet occurred.