User guide

11-13
Race Detection
b. Look for a race condition on that signal at that time. Enter:
PostRace.pl -sig signal -minmax time time2
If there is a race condition at that time on that signal, it is a
critical race condition.
The Static Race Detection Tool
It is possible for a group of statements to combine to form a loop such
that the loop will be executed more than once by other Verilog
simulators but only once by VCS. This is a race condition.
These situations come about when level sensitive “sensitivity lists”
(event controls that immediately following the always keyword in an
always block and which also do not contain the posedge or
negedge keywords) and procedural assignment statements in these
always blocks combine with other statements, such as continuous
assignment statements or module instantiation statements, to form a
potential loop. We have found that these situations do not occur if
these always blocks contain delays or other timing information, non-
blocking assignment statements, or PLI calls through user-defined
system tasks.
You start the static race detection tool with the +race=all
compile-time option (not the +race compile-time option).
After compilation the static race detection tool writes the file named
race.out.static that reports on the race conditions it finds.
The following is a excerpt from a line numbered source code example
that shows such an always block that combines with other
statements to form a loop: