User guide

11-4
Race Detection
Therefore even when a Verilog design appears to be simulating
correctly and you see the results you want, you should look for race
conditions and remove them so that you will continue to see the same
simulation results from an unrevised design well into the future. Also
you should look for race conditions while a design is in development.
VCS can help you find these race conditions by writing report files
about the race conditions in your design.
VCS writes the reports at runtime but you enable race detection at
compile-time with a compile-time option.
The reports can be lengthy for large designs. You can post-process
the report to generate another shorter report that is limited, for
example, to only part of the design or to only between certain
simulation times.
Enabling Race Detection
When you compile your design you can enable race detection during
simulation for your entire design or part of your design.
The +race compile-time option enables race detection for your entire
design.
The +racecd compile-time option enables race detection for the part
of your design that is enclosed between the ‘race and ‘endrace
compiler directives.