User guide

11-3
Race Detection
In this example, at simulation time 5, different initial blocks assign
0 and 1 to signal a. When simulation time 5 is over you do not
know if signal a’s value is 0 or 1.
Finding these race conditions is important because in Verilog
simulation you cannot control the order of execution of statements in
different always or initial blocks or continuous assignments that
execute at the same simulation time. This means that a race condition
can produce different simulation results when you simulate a design
with different, but both properly functioning, Verilog simulators.
Even worse, a race condition can result in different simulation results
with different versions of a particular simulator, or with different
optimizations or performance features of the same version of a
simulator.
Also sometimes modifications in one part of a design can cause
hidden race conditions to surface even in unmodified parts of a
design, thereby causing different simulation results from the
unmodified part of the design.
The indications of a race condition are the following:
• When simulation results do not match when comparing simulators
• When design modifications cause inexplicable results
• When simulation results do not match between different
simulation runs of the same simulator, when different versions or
different optimization features of that simulator are used