User guide

10-2
Post-Processing
• Line Tracing
• Delta Cycle
• Verilog HDL offers the advantage of having the ability to access
any internal signals from any other hierarchical block without
having to route it through the user interface.
• You can generate an EVCD file using the $dumpports or
$lsi_dumports system tasksSee “Verilog HDL offers the
advantage of having the ability to access any internal signals from
any other hierarchical block without having to route it through the
user interface.” on page 10-4.
VPD
You can create a single VPD file for the entire design using the
$vcdpluson system task. To create a dump file, use the $dumpvars
system task. To enable post-processing for the design, use the -PP
option as a compile-time option.
Delta Dumping Supported in VPD Files
VCS supports delta dumping in VPD files for post-processing using
the $vcdplusdeltacycleon system task.
The $vcdplusevent system task displays, in DVE, a symbol on the
signal’s waveform and in the Logic Browser. The event_name
argument appears in the status bar when you click on the symbol.
E|W|I specifies severity. E for error, displays a red symbol, W for
warning, displays a yellow symbol, I for information, displays a green
symbol.