User guide

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VCD and VPD File Utilities
Generating Source Files From VCD Files
The vcat utility can generate Verilog source files that are one of the
following:
• A module definition that succinctly models how a module instance
is driven by a design, that is, a concise testbench module that
instantiates the specified instance and applies stimulus to that
instance the way the entire design does. This is called testbench
generation.
• A module definition that mimics the behavior of the specified
instance to the rest of the design, that is, it has the same output
ports as the instance and in this module definition the values from
the VCD file are directly assigned to these output ports. This is
called module generation.
Note:
The vcat utility can only generate these source files for instances
of module definitions that do not have inout ports.
Testbench generation enables you to focus on a module instance,
applying the same stimulus as the design does but at faster simulation
because the testbench is far more concise than the entire design.
You can substitute module definitions at different levels of abstraction
and use vcdiff to compare the results.
Module generation enables you to use much faster simulating
“canned” modules for a part of the design to enable the faster
simulation of other parts of the design that need investigation.