User guide

xvii
Verilog Design Containing SystemC Leaf Modules. . . . . . . . . . . 19-6
Input Files Required. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
Generating the Wrapper for SystemC Modules . . . . . . . . . . . 19-8
Instantiating the Wrapper and Coding Style. . . . . . . . . . . . . . 19-11
Controlling Time Scale and Resolution in a
SystemC Module Contained in a Verilog Design . . . . . . . 19-13
Compiling a Verilog Design Containing SystemC Modules . . 19-14
Using GNU Compilers on Sun Solaris . . . . . . . . . . . . . . . 19-14
Using GNU Compilers on Linux . . . . . . . . . . . . . . . . . . . . 19-15
SystemC Designs Containing Verilog Modules . . . . . . . . . . . . . . 19-15
Input Files Required. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
Generating the Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
Instantiating the Wrapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19
Compiling a SystemC Design Containing Verilog Modules . . 19-20
Elaborating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
Considerations for Export DPI Tasks . . . . . . . . . . . . . . . . . . . 19-22
Use syscan -export_DPI <function-name>. . . . . . . . . . . . 19-22
Use a Stubs File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23
Specifying Runtime Options to the SystemC Simulation . . . . 19-24
Using GNU Compilers on SUN Solaris . . . . . . . . . . . . . . 19-25
Using GNU Compilers on Linux . . . . . . . . . . . . . . . . . . . . 19-25
Using a Port Mapping File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26
Using a Data Type Mapping File . . . . . . . . . . . . . . . . . . . . . . . . . 19-27
Debugging the SystemC Portion of a Design . . . . . . . . . . . . . . . 19-29
Debugging the Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29
Debugging Both the Verilog and SystemC Portions of a Design. 19-30