User guide

4-18
Simulating Your Design
• combinational logic including gates or built-in primitives and
continuous assignment statements
• user-defined tasks
• user-defined functions
• module instance ports
• user-defined primitives (UDPs)
• Any Verilog code protected by encryption
Ports use simulation time particularly when there are expressions in
port connection lists such as bit or part selects and concatenation
operators.
This view has separate sections for the Verilog constructs for each
module definition in the module view.