User guide

4-17
Simulating Your Design
• There are 10,000 instances of module FD2. The number of
instances is a way to assess the CPU times used by these
instances. For example, as in this case, a high CPU time with a
correspondingly high number of instances tells you that each
instance isn’t using very much CPU time.
• The module header, the first line of the module definition, is in
source file design.v on line 142.
The Program View
The program view shows the simulation time used by the testbench
program, the number of instances, and the line number where is starts
in its source file.
Example 4-4 Program View
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PROGRAM VIEW
==============================================================================
Program(index) %Totaltime No of Instances Definition
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test (1) 21.17 1 /u/design/test.sv:25.
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The Module to Construct Mapping View
This view shows you the CPU time used by different types of Verilog
constructs in each module definition in the module view. There are
the following types of Verilog constructs:
• always constructs (commonly called always blocks)
• initial constructs (commonly called initial blocks)
• module path delays in specify blocks
• timing check system tasks in specify blocks