User guide

4-15
Simulating Your Design
The Top Level View
This view shows you how much CPU time was used by:
• Any PLI application that executes along with VCS
• VCS for writing VCD and VPD files
• VCS for internal operations that can’t be attributed to any part of
your design
• The Verilog modules in your design
• A SystemVerilog testbench program block, if used
Example 4-2 Top Level View
===========================================================================
TOP LEVEL VIEW
===========================================================================
TYPE %Totaltime
---------------------------------------------------------------------------
DPI 0.00
PLI 0.00
VCD 0.00
KERNEL 29.06
MODULES 51.87
PROGRAMS 21.17
PROGRAM GC 1.64
---------------------------------------------------------------------------
In this example there is no PLI application and VCS does not write a
VCD or VPD file. VCS used 51.87% of the CPU time to simulate the
design, 21.94% for a testbench program, and 29.06% for internal
operations, such as scheduling, that VCS cannot attribute to any part
of the design. The designation KERNEL is for these internal
operations. PROGRAM GC is for the garbage collector.
The designation VCD is for the simulation time used by the callback
mechanisms inside VCS for writing either VCD or VPD files.