User guide

4-14
Simulating Your Design
For memory usage it reports the following:
• The amount of memory and the percentage of memory used by
the VCS kernel, the design, the SystemVerilog testbench program
block, cosimulation applications using either the DPI or PLI, and
the time spent writing a VCD or VPD file.
• The amount of memory and the percentage of memory that each
module definition uses.
You can use this information to see where in your design you might
be able to modify your code for faster simulation performance.
The profile data in the vcs.prof file is organized into a number of
“views” of the simulation. The vcs.prof file starts with views on CPU
time, followed by views on memory usage.
CPU Time Views
The views on CPU time are as follows:
• The Top Level View
• The Module View
• The Program View
• The Instance View
• The Program to Construct Mapping View
• The Top Level Construct View
• The Construct View Across Design