User guide

4-13
Simulating Your Design
Runtime options that specify writing to a file slow down simulation.
These runtime options are as follows:
-a filename
Appends all output of the simulation to the specified file as well
as sends it to the standard output.
-l filename
Writes all output of the simulation to the specified file as well as
to the standard output.
Other runtime options that specify operations other than the default
operations also slow down simulation to some extent.
Profiling the Simulation
If you include the +prof compile-time option when you compile your
design, VCS generates the vcs.prof file during simulation. This file
contains a profile of the simulation in terms of the CPU time and
memory that it uses.
For CPU time it reports the following:
• The percentage of CPU time used by the VCS kernel, the design,
the SystemVerilog testbench program block, cosimulation
applications using either the DPI or PLI, and the time spent writing
a VCD or VPD file.
• The module instances in the hierarchy that use the most CPU time
• The module definitions whose instances use the most CPU time
• The Verilog constructs in those instances that use the most CPU
time