User guide

4-12
Simulating Your Design
With other Verilog simulators there are two possibilities at time 0:
• The simulator executes the initial block first, initializing reg rst,
then the simulator evaluates the event control sensitivity list for
the always block and executes the always block because the
simulator initialized rst.
• The simulator evaluates the event control sensitivity list for the
always block, and so far reg rst has not changed value during
this time step so the simulator does not execute the always block.
Then the simulator executes the initial block and initializes rst.
When this happens the simulator does not re-evaluate the event
control sensitivity list for the always block.
Improving Performance
When you simulate your design you can look for ways to improve the
simulation performance. There are runtime options that enable VCS
to simulate faster or slower.
Some runtime options enable VCS to simulate your design faster
because they allow VCS to skip certain operations. You should
consider using these runtime options. They are as follows:
+vcs+ignorestop
Tells VCS to ignore the $stop system tasks in your source code.
+notimingcheck
Disables timing check system tasks. Using this option at compile
time results in even faster simulation than using it at runtime.