User guide

4-11
Simulating Your Design
How VCS Prevents Time 0 Race Conditions
At simulation time 0, VCS always executes the always blocks in which
any of the signals in the event control expression, that follows the
always keyword (the sensitivity list), initializes at time 0.
For example, consider the following code:
module top;
reg rst;
wire w1,w2;
initial
rst=1;
bottom bottom1 (rst,w1,w2);
endmodule
module bottom (rst,q1,q2);
output q1,q2;
input rst;
reg rq1,rq2;
assign q1=rq1;
assign q2=rq2;
always @ rst
begin
rq1=1’b0;
rq2=1’b0;
$display("This always block executed!");
end
endmodule