User guide

4-7
Simulating Your Design
For example, if you load a memory image with $loadmemb at the
beginning of the simulation and want to be able to restart from a
checkpoint with a different memory image, you must add Verilog code
to load the memory image after every $save call. This ensures that
at the beginning of any restart the correct memory image is loaded
before simulation begins. A reasonable way to manage this is to
create a task to handle processing arguments, and call this task at
the start of execution, and after each save.
A more detailed example follows to illustrate this. The first run
optimizes simulation speed by omitting the +dump flag. If a bug is
found, the latest checkpoint file is run with the +dump flag to enable
signal dumping.
// file test.v
module dumpvars();
task processargs;
begin
if ($test$plusargs("dump")) begin
$dumpvars;
end
end
end task
//normal start comes here
initial begin
processargs;
end
// checkpoint every 1000 time units
always
#1000 begin
// save some old restarts
$system("mv -f save.1 save.2");
$system("mv -f save save.1");
$save("save");
#0 processargs;
end
endmodule
// The design itself here
module top();
.....
endmodule