User guide

4-2
Simulating Your Design
Running and Controlling a Simulation
This section describes how to simulate your design using the binary
executable generated during compilation.
Invoking a Simulation at the Command Line
To invoke the simulation, enter the following at the command line:
% executable [options]
The options are more than one runtime options that enable you to
control how VCS executes the simulation. For a complete list of VHDL
and Verilog runtime options, see Appendix C, "Simulation Options".
You control and monitor the simulation by using UCLI, CLI or SCL
commands. Detailed descriptions of these commands are available
in Chapter 8, "Unified Command-Line Interface (UCLI)" and Chapter
9, "Using the Old Command Line Interface (CLI)"
Invoking a Simulation From DVE
To open DVE and start the simulation, do the following:
1. From the command line, open DVE.
% dve