User guide

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Compiling and Elaborating Your Design
The -top compile-time option requires the +v2k or -sverilog
compile-time option and the -new_dr compile-time option.
If you have coded your design to have more than one top-level module
you can enter more than one -top option, or you can append
arguments to the option using the plus delimiter, for example:
-top top_cfg+test+
Using the -top options tells VCS not to create extraneous top-level
modules, one that you don’t specify.
Limitations of Configurations
In the current implementation V2K configurations have the following
limitations:
• You cannot specify source code for user-defined primitives in a
configuration.
• The VPI functionality, described in section 13.6 "Displaying library
binding information" in the Std 1364-2001 IEEE Veerilog Harware
Description LRM, is not implemented.