User guide

3-52
Compiling and Elaborating Your Design
particular instances in a subhierarchy, then you can define a
configuration for a higher level of the design.
Suppose, for example, a subhierarchy of a design was an eight-bit
adder and you have RTL Verilog code describing the adder in a logical
library named rtllib and you had gate-level code describing the adder
in a logical library named gatelib. Now for some reason, you want the
gate-level code used for the 0 (zero) bit of the adder and the RTL
level code used for the other seven bits. The configuration would be
something like this:
config cfg1;
design aLib.eight_adder;
default liblist rtllib;
instance adder.fulladd0 liblist gatelib;
endconfig
Now you are going to instantiate this eight-bit adder eight times to
make a 64 bit adder. You want to use configuration cfg1 for the first
instance of the eight-bit adder but not in any other instance. A
configuration to do so would be as follows:
config cfg2;
design bLib.64_adder;
default liblist bLib;
instance top.64add0 use work.cfg1:config;
endconfig
The -top Compile-Time Option
VCS has the -top compile-time option for specifying the
configuration that describes the top-level configuration or module of
the design, for example:
vcs -top top_cfg +v2k -new_dr ...
vcs -top test -sverilog -new_dr ...