User guide

3-49
Compiling and Elaborating Your Design
• Specifies overrides to the logical library search order for all
instances of specified cells
You can define a configuration in a library mapping file or in any type
of Verilog source file.
Configurations can be mapped to a logical library just like any other
type of cell.
Configuration Syntax
A configuration contains the following statements:
config config_identifier;
design [library_identifier.]cell_identifier;
config_rule_statement;
endconfig
Where:
config
Is the keyword that begins a configuration.
config_identifier
Is the name you enter for the configuration.
design
Is the keyword that starts a design statement for specifying the
top of the design.
[library_identifier.]cell_identifier;
Specifies the top-level module (or top-level modules) in the design
and the logical library for this module (modules).
config_rule_statement
Zero, one, or more of the following clauses: default, instance,
or cell.