User guide

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Compiling and Elaborating Your Design
Resolving ‘include Compiler Directives
The source file in a logical library might include the ‘include
compiler directive. if so, you can include the -incdir option on the
line in the library mapping file that declares the logical library, for
example:
library gatelib /net/design1/gatelib/*.v -incdir /net/
design1/spec1lib, /net/design1/spec2lib;
Note:
The +incdir VCS compile-time option, on the vcs command
line, overrides the -incdir option in the library mapping file.
Configurations
Verilog 2001 configurations are sets of rules that specify what source
code is used for particular instances.
Verilog 2001 introduces the concept of configurations and it also
introduces the concept of cells. A cell is like a VHDL design unit. A
module definition is a type of cell, but so is a user-defined primitive.
Similarly, a configuration is also a cell. A SystemVerilog interface and
testbench program block are also types of cells. A configuration uses
the concept of a cell and in fact a cell is a keyword in a configuration.
Configurations do the following:
• Specify a library search order for resolving cell instances (so can
a library mapping file)
• Specifies overrides to the logical library search order for specified
instances