User guide

3-46
Compiling and Elaborating Your Design
The following is an example of the contents of a library mapping file:
library lib1 /net/design1/design1_1/*.v;
library lib2 /net/design1/design1_2/*.v;
Note:
Path names can be absolute or relative to the current directory
that contains the library mapping file.
In this example library mapping file there are two logical libraries. VCS
searches the source code assigned to lib1 first to resolve module
instances (or user-defined primitive or SystemVerilog interface
instances) because that logical library is listed first in the library
mapping file.
When you use a library mapping file, source files that are not assigned
to a logical library in this file are assigned to the default logical library
named work.
You specify the library mapping file with the -libmap compile-time
option. Using a library mapping file is a Verilog 2001 feature so when
you use it you must also include the +v2k or -sverilog compile-
time option.
The paths to the Verilog source files in these logical libraries must
also be included on the vcs command line. For example:
vcs +v2k dev.v -libmap lib1.map /net/design1/design1_1/
indev.v /net/design1/design1_2/indev.v
Both the /net/design1/design1_1 and the /net/design1/design1_2
directories contain a file named indev.v for a module named indev,
but VCS uses the module in lib1 to resolve instances in dev.v and the
other module named indev is a second and extraneous top-level
module.